1. The Case for a New SOC Design Methodology
1.1 The Age of Megagate SOCs
1.2 The Fundamental Trends of SOC Design
1.3 What’s Wrong with Today’s Approach to SOC Design?
1.4 Preview: An Improved Design Methodology for SOC Design
1.5 Further Reading
2. SOC Design Today
2.1 Hardware System Structure
2.2 Software Structure
2.3 Current SOC DesignFlow
2.4 The Impact of Semiconductor Economics
2.5 Six Major Issues in SOC Design
2.6 Further Reading.
3. A New Look at SOC Design
3.1 Accelerating Processors for Traditional Software Tasks
3.2 Example: Tensilica Xtensa Processors for EEMBC Benchmarks
3.3 System Design with Multiple Processors
3.4 New Essentials of SOC Design Methodoloy
3.5 Addressing the Six Problems
3.6 Further Reading
4. System-Level Design of Complex SOCs
4.1 Complex SOC System Architecture Opportunities
4.2 Major Decisions in Processor-Centric SOC Organization
4.3 Communication Design = Software Mode + Hardware Interconnect
4.4 Hardware Interconnect Mechanisms
4.5 Performance-Driven Communication Design
4.6 The SOC Design Flow
4.7 Non-Processor Building Blocks in Complex SOC
4.8 Implications of Processor-Centric SOC Architecture
4.9 Further Reading
5. Configurable Processors: A Software View
5.1 Processor Hardware/Software Cogeneration
5.2 The Process of Instruction Definition and Application Tuning
5.3 The Basics of Instruction Extension
5.4 The Programmer’s Mode
5.5 Processor Performance Factors
5.6 Example: Tuning a Large Task
5.7 Memory-System Tuning
5.8 Long Instruction Words
5.9 Fully Automatic Instruction-Set Extension
5.10 Further Reading
6. Configurable Processors: A Hardware View
6.1 Application Acceleration: A Common Problem
6.2 Introduction to Pipelines and Processors
6.3 Hardware Blocks to Processors
6.4 Moving from Hardwired Engines to Processors
6.5 Designing the Processor Interface
6.6 A Short Example: ATM Packet Segmentation and Reassembly
6.7 Novel Roles for Processors in Hardware Replacement
6.8 Processors, Hardware Implementation, and Verification Flow
6.9 Progress in Hardware Abstraction
6.10 Further Reading
7. Advanced Topics in SOC Design
7.1 Pipelining for Processor Performance
7.2 Inside Processor Pipeline Stalls
7.3 Optimizing Processors to Match Hardware
7.4 Multiple Processor Debug and Trace
7.5 Issues in Memory Systems
7.6 Optimizing Power Dissipation in Extensible Processors
7.7 Essentials of TIE
7.8 Further Reading
8. The Future of SOC Design: The Sea of Processors
8.2 Why Is Software Programmability So Central?
8.3 Looking into the Future of SOC
8.4 Processor Scaling Model
8.5 Future Applications of Complex SOCs
8.6 The Future of the Complex SOC Design Process
8.7 The Future of the Industry
8.8 The Disruptive-Technology View
8.9 The Long View
8.10 Further Reading
Index